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1 for more information www.linear.com/LTC3864 typical a pplica t ion fea t ures descrip t ion 60v low i q step-down dc/dc controller with 100% duty cycle capability the lt c ? 3864 is a robust, high voltage step-down dc/dc controller optimized for automotive and industrial applica - tions. it drives a p-channel power mosfet switch allowing 100% duty cycle operation. the wide input and output volt - age ranges cover a multitude of applications. this device has been verified with the failure mode and effects analysis (fmea) procedure for operation during failure conditions. the LTC3864 offers excellent light load efficiency, draw - ing only 40a quiescent current in a user programmable burst mode operation. its peak current mode, constant frequency p wm ar chitecture provides for good control of switching frequency and output current limit. the switch - ing frequency can be programmed from 50khz to 850khz with an external resistor and can be synchronized to an external clock from 75khz to 750khz. the LTC3864 offers programmable soft-start or output tracking. safety features include over voltage protection, overcurrent and short-circuit protection including fre - quency foldback and a power good output signal. the LTC3864 is available in thermally enhanced 12-pin msop and 3mm 4mm dfn packages. 5.2v to 60v input, 5v/2a output, 350khz step-down converter a pplica t ions n wide operating v in range: 3.5v to 60v n wide v out range: 0.8v to v in n low operating i q = 40a n very low dropout operation: 100% duty cycle n strong high voltage mosfet gate driver n constant frequency current mode architecture n verified fmea for adjacent pin open/short n selectable high efficiency burst mode ? operation or pulse-skipping mode at light loads n programmable fixed frequency: 50khz to 850khz n phase-lockable frequency: 75khz to 750khz n accurate current limit n programmable soft-start or voltage t racking n internal soft-start guarantees smooth start-up n power good output voltage monitor n low shutdown i q = 7a n available in small 12-pin thermally enhanced msop and dfn packages n industrial and automotive power supplies n telecom power supplies n distributed power systems l , lt, ltc, ltm, opti-loop, linear technology, burst mode and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5731694. efficiency 350khz 100k 25m 10h cap 0.47f 10f pgnd LTC3864 3864 ta01a ss ith freq sgnd run v in pllin/mode sense gate pgood v fb 9.09k 422k 47f 2 v out * 5v 2a 80.6k v in * 5.2v to 60v 3.3nf *v out follows v in when 3.5v v in 5.2v load current (a) 0.01 50 efficiency (%) 80 70 60 90 100 0.1 1 3864 ta01b pulse-skipping burst mode operation v in = 12v v out = 5v LTC3864 3864fa
2 for more information www.linear.com/LTC3864 p in c on f igura t ion a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ......................... C0 .3v to 65v v in -v sense voltage ...................................... C0 .3v to 6v v in -v cap voltage ........................................ C 0.3v to 10v run voltage ............................................... C0.3v to 65v pgood, pllin/mode voltages ................... C 0.3v to 6v ss, ith, freq, v fb voltages ........................ C 0.3v to 5v (note 1) 12 11 10 9 8 7 13 pgnd 1 2 3 4 5 6 gate v in sense cap run pgood pllin/mode freq sgnd ss v fb ith top view de package 12-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w, jc = 5.5c/w exposed pad (pin 13) is pgnd, must be soldered to pcb for optimal thermal performance 1 2 3 4 5 6 pllin/mode freq sgnd ss v fb ith 12 11 10 9 8 7 gate v in sense cap run pgood top view 13 pgnd mse package 12-lead plastic msop t jmax = 150c, ja = 40c/w, jc = 10c/w exposed pad (pin 13) is pgnd, must be soldered to pcb for optimal thermal performance o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC3864emse#pbf LTC3864emse#trpbf 3864 12-lead plastic msop C40c to 125c LTC3864imse#pbf LTC3864imse#trpbf 3864 12-lead plastic msop C40c to 125c LTC3864hmse#pbf LTC3864hmse#trpbf 3864 12-lead plastic msop C40c to 150c LTC3864mpmse#pbf LTC3864mpmse#trpbf 3864 12-lead plastic msop C55c to 150c LTC3864ede#pbf LTC3864ede#trpbf 3864 12-lead (4mm 3mm) plastic dfn C40c to 125c LTC3864ide#pbf LTC3864ide#trpbf 3864 12-lead (4mm 3mm) plastic dfn C40c to 125c LTC3864hde#pbf LTC3864hde#trpbf 3864 12-lead (4mm 3mm) plastic dfn C40c to 150c LTC3864mpde#pbf LTC3864mpde#trpbf 3864 12-lead (4mm 3mm) plastic dfn C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range (notes 2, 3, 4) l tc3864e,i ....................................... C 40c to 125c lt c3864h .......................................... C4 0c to 150c lt c3864mp ....................................... C 55c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) ms op package ................................................. 3 00c LTC3864 3864fa
3 for more information www.linear.com/LTC3864 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units input supply v in input voltage operating range 3.5 60 v v uvlo undervoltage lockout (v in -v cap ) ramping up threshold (v in -v cap ) ramping down threshold hysteresis l l 3.25 3.00 3.50 3.25 0.25 3.8 3.50 v v v i q input dc supply current pulse-skipping mode pllin/mode = 0v, freq = 0v, v fb = 0.83v (no load) 0.77 1.2 ma burst mode operation pllin/mode = open, freq = 0v , v fb = 0.83v (no load) 40 60 a shutdown supply current run = 0v 7 12 a output sensing v reg regulated feedback voltage v ith = 1.2v (note 5) l 0.792 0.800 0.809 v ?v reg ?v in feedback voltage line regulation v in = 3.8v to 60v (note 5) C0.005 0.005 %/v ?v reg ?v ith feedback voltage load regulation v ith = 0.6v to 1.8v (note 5) C0.1 C0.015 0.1 % g m(ea) error amplifier transconductance v ith = 1.2v, ?i ith = 5a (note 5) 1.8 ms i fb feedback input bias current C50 C10 50 na current sensing v ilim current limit threshold (v in -v sense ) v fb = 0.77v l 85 95 103 mv i sense sense pin input current v sense = v in 0.1 2 a start-up and shutdown v run run pin enable threshold v run rising l 1.22 1.26 1.32 v v runhys run pin hysteresis 150 mv i ss soft-start pin charging current v ss = 0v 10 a switching frequency and clock synchronization f programmable switching frequency r freq = 24.9k r freq = 64.9k r freq = 105k 375 105 440 810 505 khz khz khz f lo low switching frequency freq = 0v 320 350 380 khz f hi high switching frequency freq = open 485 535 585 khz f sync synchronization frequency l 75 750 khz v clk(ih) clock input high level into pllin/mode l 2 v v clk(lo) clock input low level into pllin/mode l 0.5 v f fold foldback frequency as percentage of programmable frequency v fb = 0v, freq = 0v 18 % t on(min) minimum on-time 220 ns gate driver v cap gate bias ldo output voltage (v in -v cap ) i gate = 0ma l 7.6 8.0 8.5 v v capdrop gate bias ldo dropout voltage v in = 5v, i gate = 15ma 0.2 0.5 v ?v cap(line) gate bias ldo line regulation 9v v in 60v, i gate = 0ma 0.002 0.03 %/v ?v cap(load) gate bias ldo load regulation load = 0ma to 20ma C3.5 % the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) v in = 12v, unless otherwise noted. LTC3864 3864fa
4 for more information www.linear.com/LTC3864 symbol parameter conditions min typ max units r up gate pull-up resistance gate high 2 r dn gate pull-down resistance gate low 0.9 pgood and overvoltage v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v i pg pgood leakage current v pgood = 5v 1 a %pgd pgood trip level v fb ramping negative with respect to v reg hysteresis C13 C10 2.5 C7 % % v fb ramping positive with respect to v reg hysteresis 7 10 2.5 13 % % t pgdly pgood delay pgood going high to low pgood going low to high 100 100 s s v fbov v fb overvoltage lockout threshold gate going high without delay, v fb(ov) -v fb(nom) in percent 10 % e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) v in = 12v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the specified maximum operating junction temperature may impair device reliability or permanently damage the device. note 3: the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) as follows: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance provided in the pin configuration section for the corresponding package. note 4: the LTC3864 is tested under pulsed loading conditions such that t j t a . the LTC3864e is guaranteed to meet performance specifications from 0c to 85c operating junction temperature range. the LTC3864e specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3864i is guaranteed to meet performance specifications over the C40c to 125c operating junction temperature range, the LTC3864h is guaranteed over the C40c to 150c operating junction temperature range, and the LTC3864mp is guaranteed and tested over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 5: the LTC3864 is tested in a feedback loop that adjust v fb to achieve a specified error amplifier output voltage (on ith pin). LTC3864 3864fa
5 for more information www.linear.com/LTC3864 typical p er f or m ance c harac t eris t ics transient response: burst mode operation dropout behavior (100% duty cycle) low v in operation normal soft start-up soft start-up into a prebiased output output tracking pulse-skipping mode operation waveforms burst mode operation waveforms transient response: pulse-skipping mode operation t a = 25c, unless otherwise noted. v in = 12v, v out = 5v figure 8 circuit v out 1v/div ss 200mv/div v in 5v/div 1ms/div 3864 g07 v in = 12v, v out = 5v i load = 0.5ma figure 8 circuit ss 200mv/div v out 1v/div run 5v/div 1ms/div 3864 g08 v out prebiased to 2.9v v in = 12v, v out = 5v i load = 100ma figure 8 circuit v out 2v/div ss 200mv/div 20ms/div 3864 g09 v in transient: 12v to 4v and back to 12v v out = 5v, i load = 100ma, figure 8 circuit gate 10v/div v out 2v/div v in 2v/div 50ms/div 3864 g05 v out = v in in dropout v in = 0v to 3.8v then back to 0v i load = 100ma figure 8 circuit sw 5v/div v out 1v/div v in 1v/div 20ms/div 3864 g06 v out programmed to 5v, but starts up in dropout since v in < 5v v in = 12v v out = 5v i load = 100ma figure 8 circuit i l 500ma/div v sw 10v/div v out 50mv/div 10s/div 3864 g02 v in = 12v v out = 5v i load = 100ma figure 8 circuit i l 500ma/div v sw 10v/div v out 50mv/div 2s/div 3864 g01 v in = 12v v out = 5v transient = 100ma to 2a figure 8 circuit i l 2a/div v out 500mv/div i load 2a/div 100s/div 3864 g03 v in = 12v v out = 5v transient = 100ma to 2a figure 8 circuit i l 2a/div v out 500mv/div i load 2a/div 100s/div 3864 g04 LTC3864 3864fa
6 for more information www.linear.com/LTC3864 typical p er f or m ance c harac t eris t ics burst mode input current over input voltage (no load) pulse-skipping mode input current over input voltage (no load) shutdown current over input voltage output regulation over input voltage output regulation over load current output regulation over temperature overcurrent protection short-ciruit protection v in line transient behavior t a = 25c, unless otherwise noted. v in = 12v, v out = 5v figure 8 circuit v out 500mv/div i l 1a/div i load 1a/div 1a 1a 20ms/div 3864 g10 3.2a v out droops due to reaching current limit v in = 12v, v out = 5v figure 8 circuit i l 2a/div v out 5v/div short- circuit trigger 500s/div 3864 g11 short-circuit region soft recovery from short v in (v) 0 30 i vin (a) 35 55 50 45 40 60 65 70 10 20 30 40 3864 g13 50 60 v in = 12v, v out = 5v i load = 0a figure 8 circuit v in (v) 0 700 i vin (a) 850 800 750 900 950 10 20 30 40 3864 g14 50 60 v in = 12v, v out = 5v i load = 0a figure 8 circuit v in (v) 0 0 i vin (a) 15 10 5 20 25 10 20 30 40 3864 g15 50 60 figure 8 circuit v in = 12v, surge to 48v v out = 5v i load = 200ma, figure 8 circuit v out 50mv/div gate 20v/div v in 20v/div 2ms/div 3864 g12 v in (v) 0 ?0.010 normalized ?v out (%) 0 ?0.005 0.005 0.010 10 20 30 40 3864 g16 50 60 v out = 5v i load = 200ma v out normalized at v in = 12v figure 8 circuit burst mode operation pulse-skipping i load (a) ?0.5 ?0.010 normalized ?v out (%) 0 ?0.005 0.005 0.010 0 0.5 1 1.5 3864 g17 2 2.5 v in = 12v, v out = 5v i load normalized at i load = 1a figure 8 circuit burst mode operation pulse-skipping temperature (c) ?75 ?1.0 normalized ?v out (%) 0 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 ?25 25 75 125 3864 g18 175 v in = 12v, v out = 5v i load = 200ma v out normalized to t a = 25c figure 8 circuit burst mode operation pulse-skipping LTC3864 3864fa
7 for more information www.linear.com/LTC3864 typical p er f or m ance c harac t eris t ics gate bias ldo (v in - v cap ) load regulation gate bias ldo (v in - v cap ) dropout behavior current sense voltage over ith voltage current sense voltage over temperature ss pin pull-up current over temperature run pin pull-up current over temperature free running frequency over input voltage free running frequency over temperature frequency foldback % over feedback voltage t a = 25c, unless otherwise noted. v in (v) 0 300 f (khz) 450 600 550 500 400 350 10 20 30 40 50 3864 g19 60 freq = 0v freq = open v fb (mv) 0 0 frequency foldback % 60 120 100 80 40 20 200 400 600 3864 g21 800 i gate (ma) 0 ?3.5 (v in - v cap ) regulation (%) ?2.0 0.5 ?1.0 ?0.5 0.0 ?1.5 ?2.5 ?3.0 5 10 15 3864 g22 20 i gate (ma) 0 ?0.5 (v in - v cap ) dropout (v) 0.1 v in = 5v ?0.1 0.0 ?0.2 ?0.3 ?0.4 5 10 15 3864 g23 20 temperature (c) ?75 90 current limit sense voltage (mv) 100 98 94 92 96 ?25 25 75 125 3864 g25 175 temperature (c) ?75 0.25 run pull-up current (a) 0.65 0.55 0.35 0.45 ?25 25 75 125 3864 g27 175 temperature (c) ?75 300 f (khz) 450 600 550 500 400 350 ?25 25 75 125 3864 g20 175 freq = 0v freq = open temperature (c) ?75 6 ss pull-up current (v) 14 12 8 10 ?25 25 75 125 3864 g26 175 ith voltage (v) 0 ?10 current sense voltage (mv) 100 80 90 40 30 20 10 0 70 60 50 0.4 0.8 1.2 1.6 3864 g24 2 burst mode operation pulse-skipping LTC3864 3864fa
8 for more information www.linear.com/LTC3864 p in func t ions pllin/mode (pin 1): external reference clock input and burst mode enable/disable. when an external clock is applied to this pin, the internal phase-locked loop will synchronize the turn-on edge of the gate drive signal with the rising edge of the external clock. when no external clock is applied, this input determines the operation during light loading. floating this pin selects low i q (40a) burst mode operation. pulling to ground selects pulse-skipping mode operation. freq (pin 2): switching frequency set point input. the switching frequency is programmed by an external set- point resistor r freq connected between the freq pin and signal ground. an internal 20a current source creates a voltage across the external setpoint resistor to set the internal oscillator frequency. alternatively, this pin can be driven directly by a dc voltage to set the oscillator frequency. grounding selects a fixed operating frequency of 350khz. floating selects a fixed operating frequency of 535khz. sgnd (pin 3): ground reference for small signal analog component (signal ground). signal ground should be used as the common ground for all small signal analog inputs and compensation components. connect signal ground to power ground (ground reference for power components) only at one point using a single pcb trace. ss (pin 4): soft-start and external tracking input. the LTC3864 regulates the feedback voltage to the smaller of 0.8v or the voltage on the ss pin. an internal 10a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to the final regulated output voltage. alternatively , another voltage supply con - nected through a resistor divider to this pin allows the output to track the other supply during start-up. v fb (pin 5): output feedback sense. a resistor divider from the regulated output point to this pin sets the output voltage. the LTC3864 will nominally regulate v fb to the internal reference value of 0.8v. if v fb is less than 0.4v, the switching frequency will linearly decrease and fold back to about one-fifth of the internal oscillator frequency to reduce the minimum duty cycle. ith (pin 6): current control threshold and controller compensation point. this pin is the output of the error amplifier and the switching regulators compensation point. the voltage ranges from 0v to 2.9v, with 0.8v cor - responding to zero sense voltage (zero current). pgood (pin 7): power good indicator output. this open drain logic output is pulled to ground when the output voltage is outside of a 10% window around the regulation point. the pgood switches states only after a 100s delay . run (pin 8): digital run control input. a run voltage above the 1.26v threshold enables normal operation, while a voltage below the threshold shuts down the controller. an internal 0.4a current source pulls the run pin up to about 3.3v. the run pin can be connected to an external power supply up to 60v. cap (pin 9): gate driver (C) supply. a low esr ceramic bypass capacitor of at least 0.47f or 10x the effective c miller of the p-channel power mosfet, is required from v in to this pin to serve as a bypass capacitor for the in - ternal regulator. to insure stable low noise operation, the bypass capacitor should be placed adjacent to the v in and cap pins and connected using the same pcb metal layer. sense (pin 10): current sense input. a sense resistor r sense from v in pin to the sense pin sets the maximum current limit. the peak inductor current limit is equal to 95mv/r sense . for accuracy, it is important that the v in pin and the sense pin route directly to the current sense resistor and make a kelvin (4-wire) connection. v in (pin 11): chip power supply. a minimum bypass capacitor of 0.1f is required from the v in pin to power ground. for best performance use a low esr ceramic capacitor placed near the v in pin. gate (pin 12): gate drive output for external p-channel mosfet. the gate driver bias supply voltage (v in -v cap ) is regulated to 8v when v in is greater than 8v. the gate driver is disabled when (v in -v cap ) is less than 3.5v (typi - cal), 3.8v maximum in startup and 3.25v (typical) 3.5v maximum in normal operation. pgnd (exposed pad pin 13): ground reference for power components (power ground). the pgnd exposed pad must be soldered to the circuit board for electrical contact and for rated thermal performance of the package. connect signal ground to power ground only at one point using a single pcb trace. LTC3864 3864fa
9 for more information www.linear.com/LTC3864 ? + ea (g m = 1.8ms) 0.8v 10a logic control ldo in out pll system q s r mode/clock detect delay 100s vco ov o.88v slope compensation o.72v uv 3.25v gate cap ss v fb v in ? 8v sense v in 1.26v ? + + r pgd pllin/mode pgnd c cap mp d1 v out uvlo r freq sgnd freq run run 0.4a 20a 3864 fd + ? ? + ? drv clock pgood + ? + ? o.425v burst mode operation + ? ith r ith c ith1 l c ss c in v in r sense c out v out r fb2 r fb1 icmp + f unc t ional diagra m LTC3864 3864fa
10 for more information www.linear.com/LTC3864 o pera t ion main control loop (refer to functional diagram) the LTC3864 uses a peak current-mode control architec - ture to regulate the output in an asynchronous step-down dc/dc switching regulator. the v fb input is compared to an internal reference by a transconductance error ampli - fier (ea). the internal reference can be either a fixed 0.8v reference v ref or the voltage input on the ss pin. in normal operation v fb regulates to the internal 0.8v reference voltage. in soft-start or tracking mode, when the ss pin voltage is less than the internal 0.8v reference voltage, v fb will regulate to the ss pin voltage. the error amplifier output connects to the ith (current [i] threshold [th]) pin. the voltage level on the ith pin is then summed with a slope compensation ramp to create the peak inductor current set point. the peak inductor current is measured through a sense resistor r sense placed across the v in and sense pins. the resultant differential voltage from v in to sense is proportional to the inductor current and is compared to the peak inductor current set point. during normal operation the p-channel power mosfet is turned on when the clock leading edge sets the sr latch through the s input. the p-channel mosfet is turned off through the sr latch r input when the differential voltage from v in to sense is greater than the peak inductor current set point and the current comparator, icmp, trips high. power cap and v in undervoltage lockout (uvlo) power for the p-channel mosfet gate driver is derived from the cap pin. the cap pin is regulated to 8v below v in in order to provide efficient p-channel operation. the power for the v cap supply comes from an internal ldo, which regulates the v in -cap differential voltage. a mini - mum capacitance of 0.47f (low esr ceramic) is required between v in and cap to assure stability. for v in 8v, the ldo will be in dropout and the cap volt - age will be at ground, i.e. the v in -cap differential voltage will equal v in . if v in -cap is less than 3.25v (typical), the LTC3864 enters a uvlo state where the gate is prevented from switching and most internal circuitry is shut down. in order to exit uvlo, the v in -cap voltage would have to exceed 3.5v (typical). shutdown and soft-start when the run pin is below 0.7v, the controller and most internal circuits are disabled. in this micropower shutdown state, the LTC3864 draws only 7a. releasing the run pin allows a small internal pull up current to pull the run pin above 1.26v and enable the controller. the run pin can be pulled up to an external supply of up to 60v or it can be driven directly by logic levels. the start-up of the output voltage v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the 0.8v internal reference, the v fb pin is regulated to the voltage on the ss pin. this allows the ss pin to be used to program a soft-start by connecting an external capacitor from the ss pin to signal ground. an internal 10a pull-up current charges this capacitor, creat - ing a voltage ramp on the ss pin. as the ss voltage rises from 0v to 0.8v , the output voltage v out rises smoothly from zero to its final value. alternatively, the ss pin can be used to cause the start- up of v out to track that of another supply. typically, this requires connecting the ss pin to an external resistor divider from the other supply to ground. (see applications information section.) under shutdown or uvlo, the ss pin is pulled to ground and prevented from ramping up. if the slew rate of the ss pin is greater than 1.2v/ms, the output will track an internal soft-start ramp instead of the ss pin. the internal soft-start will guarantee a smooth start-up of the output under all conditions, including in the case of a short-circuit recovery where the output voltage will recover from near ground. light load current operation (burst mode operation or pulse-skipping mode) the LTC3864 can be enabled to enter high efficiency burst mode operation or pulse-skipping mode at light loads. to select pulse-skipping operation, tie the pllin/mode pin to signal ground. to select burst mode operation, float the pllin/mode pin. in burst mode operation, if the v fb is higher than the refer - ence voltage, the error amplifier will decrease the voltage on the ith pin. when the ith voltage drops below 0.425v , LTC3864 3864fa
11 for more information www.linear.com/LTC3864 o pera t ion the internal sleep signal goes high, enabling sleep mode. the ith pin is then disconnected from the output of the error amplifier and held at 0.55v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current to 40a while the load current is supplied by the output capacitor. as the output voltage and hence the feedback voltage decreases, the error amplifiers output will rise. when the output voltage drops enough, the ith pin is reconnected to the output of the error amplifier, the sleep signal goes low, and the controller resumes normal operation by turning on the external p-mosfet on the next cycle of the internal oscil - lator. in burst mode operation, the peak inductor current has to reach at least 25% of current limit for the current comparator, icmp , to trip and turn the p-mosfet back off, even though the ith voltage may indicate a lower current setpoint value. when the pllin/mode pin is connected for pulse-skipping mode, the LTC3864 will skip pulses during light loads. in this mode, icmp may remain tripped for several cycles and force the external mosfet to stay off, thereby skipping pulses. this mode offers the benefits of smaller output ripple, lower audible noise, and reduced rf interference, at the expense of lower efficiency when compared to burst mode operation. frequency selection and clock synchronization the switching frequency of the LTC3864 can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to signal ground, floated, or programmed through an external resistor. tying freq pin to signal ground selects 350khz, while floating selects 535khz. placing a resistor between freq pin and signal ground allows the frequency to be programmed between 50khz and 850khz. the phase-locked loop (pll) on the LTC3864 will syn - chronize the internal oscillator to an external clock source when connected to the pllin/mode pin. the pll for ces the turn-on edge of the external p-channel mosfet to be aligned with the rising edge of the synchronizing signal. the oscillator s default frequency is based on the operating frequency set by the freq pin. if the oscillators default frequency is near the external clock frequency, only slight adjustments are needed for the pll to synchronize the external p-channel mosfets turn-on edge to the rising edge of the external clock. this allows the pll to lock rapidly without deviating far from the desired frequency. the pll is guaranteed from 75khz to 750khz. the clock input levels should be greater than 2v for hi and less than 0.5v for lo. power good and fault protection the pgood pin is an open-drain output. an internal n-channel mosfet pulls the pgood pin low when the v fb pin voltage is outside a 10% window from the 0.8v internal voltage reference. the pgood pin is also pulled low when the run pin is low (shut down). when the v fb pin voltage is within the 10% window, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. the pgood open-drain output has a 100s delay before it can transition states. when the v fb voltage is above +10% of the regulated voltage of 0.8v, this is considered as an overvoltage con - dition and the external p-mosfet is immediately turned off and prevented from ever turning on until v fb returns below +7.5%. in the event of an output short circuit or overcurrent con - dition that causes the output voltage to drop significantly while in current limit, the LTC3864 operating frequency will fold back. anytime the output feedback v fb voltage is less than 50% of the 0.8v internal reference (i.e., 0.4v), frequency foldback is active. the frequency will continue to drop as v fb drops until reaching a minimum foldback frequency of about 18% of the setpoint frequency. fre - quency foldback is designed, in combination with peak current limit, to limit current in start-up and short-cir cuit conditions. setting the foldback frequency as a per centage of operating frequency assures that start-up characteristics scale appropriately with operating frequency. LTC3864 3864fa
12 for more information www.linear.com/LTC3864 the LTC3864 is a current mode, constant frequency pwm controller for an asynchronous step-down dc/dc regulator with a p-channel power mosfet acting as the main switch and a schottky power diode acting as the commutating (catch) diode. the input range extends from 3.5v to 60v. the output range can be programmed from 0.8v to all the way up to v in . the LTC3864 can transition from regulation to 100% duty cycle when the input voltage drops below the programmed output voltage. additionally, the LTC3864 offers burst mode operation with 40a quiescent current, which delivers outstanding efficiency in light load opera - tion. the LTC3864 is a low pin count, robust and easy to use solution in applications which require high efficiency and operate with widely var ying high voltage inputs. the typical application on the front page is a basic l tc3864 application circuit. the LTC3864 can sense the inductor current through a high side series sense resistor, r sense , placed between v in and the source of the external p- mosfet. once the required output voltage and operating frequency have been determined, external component selection is driven by load requirements, and begins with the selection of inductor and r sense . next, the power mosfet and catch diode are selected. finally, input and output capacitors are selected. output voltage programming the output voltage is programmed by connecting a feedback resistor divider from the output to the v fb pin as shown in figure 1. the output voltage in steady state operation is set by the feedback resistors according to the equation: v out = 0.8v ? 1+ r fb2 r fb1 ? ? ? ? ? ? to improve the transient response, a feedforward capacitor c ff may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the gate signal that drives the external p-mosfet. a pplica t ions i n f or m a t ion switching frequency and clock synchronization the choice of operating frequency is a trade-off between efficiency and component size. lowering the operating fre - quency improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. conversely, raising the operating frequency degrades efficiency but reduces component size. the l tc3864 can free run at a user programmed switch - ing frequency, or it can synchronize with an external clock to run at the clock frequency. when the l tc3864 is synchronized, the gate pin will phase synchronize with the rising edge of the applied clock in order to turn the external p-mosfet on. the switching frequency of the LTC3864 is programmed with the freq pin, and the external clock is applied at the pllin/mode pin. table 1 highlights the different states in which the freq pin can be used in conjunction with the pllin/mode pin. table 1 freq pin pllin/mode pin frequency 0v dc voltage 350khz floating dc voltage 535khz resistor to gnd dc voltage 50khz to 850khz any of the above external clock phase locked to external clock LTC3864 v fb v out r fb2 c ff r fb1 3864 f01 figure 1. setting the output voltage LTC3864 3864fa
13 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion the free-running switching frequency can be programmed from 50khz to 850khz by connecting a resistor from freq pin to signal ground. the resulting switching frequency as a function of resistance on freq pin is shown in figure 2. set the free-running frequency to the desired synchroni - zation frequency using the freq pin so that the internal oscillator is prebiased to approximately the synchronization frequency . while it is not required that the free-running frequency be near the external clock frequency, doing so will minimize synchronization time. inductor selection the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency generally results in lower efficiency because of mosfet gate charge and transition losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. given the desired input and output voltages, the inductor value and operation frequency determine the ripple current: ? i l = v out f ? l ? ? ? ? ? ? 1? v out v in ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and results in lower output ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3864 f02 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 figure 2. switching frequency vs resistor on freq pin this requires a large inductor. there is a trade-off between component size, efficiency, and operating frequency. a reasonable starting point for ripple current is 40% of i out(max) at nominal v in . the largest ripple current occurs at the highest v in . to guarantee that the ripple current does not exceed a specified maximum, the inductance should be chosen according to: l = v out f ? ? i l(max) ? ? ? ? ? ? 1? v out v in(max) ? ? ? ? ? ? once the inductance value has been determined, the type of inductor must be selected. core loss is independent of core size for a given inductor value, but it is very depen - dent on the inductance selected. as inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. high efficiency converters generally cannot tolerate the core loss of low cost powdered iron cores, forcing the use of more expensive ferrite materials. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on cop - per loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this will result in an abrupt increase in inductor ripple current and output voltage ripple. do not allow the core to saturate! a variety of inductors are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft, toko, vishay , pulse, and wrth. current sensing and current limit programming the LTC3864 senses the inductor current through a cur - rent sense resistor, r sense , placed across the v in and sense pins. the voltage across the resistor, v sense , is proportional to inductor current and in normal operation is compared to the peak inductor current setpoint. a current limit condition is detected when v sense exceeds 95mv. when the current limit threshold is exceeded, the p-channel mosfet is immediately turned off by pulling the gate voltage to v in regardless of the controller input. LTC3864 3864fa
14 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion the peak inductor current limit is equal to: i l(peak) ? 95mv r sense ? ? ? ? ? ? this inductor current limit would translate to an output current limit based on the inductor ripple: i limit ? 95mv r sense ? ? i l 2 the sense pin is a high impedance input with a maximum leakage of 2a. since the LTC3864 is a peak current mode controller, noise on the sense pin can create pulse width jitter. careful attention must be paid to the layout of r sense . to ensure the integrity of the current sense signal, v sense , the traces from v in and sense pins should be short and run together as a differential pair and kelvin (4-wire) connected across r sense (figure 3). drain current i d(max) , and the mosfets thermal resistance jc(mosfet) and ja(mosfet) . the gate driver bias voltage v in -v cap is set by an internal ldo regulator. in normal operation, the cap pin will be regulated to 8v below v in . a minimum 0.1f capacitor is required across the v in and cap pins to ensure ldo stability. if required, additional capacitance can be added to accommodate higher gate currents without voltage droop. in shutdown and burst mode operation, the cap ldo is turned off. in the event of cap leakage to ground, the cap voltage is limited to 9v by a weak internal clamp from v in to cap. as a result, a minimum 10v v gs rated mosfet is required. the power dissipated by the p-channel mosfet when the LTC3864 is in continuous conduction mode is given by: p mosfet ? d ? i out 2 ? t ? r ds(on) + v in 2 ? i out 2 ? ? ? ? ? ? ? c miller ( ) ? r dn v in ? v cap ( ) ? v miller + r up v miller ? ? ? ? ? ? ? f where d is duty factor, r ds(on) is on-resistance of p-mosfet, t is temperature coefficient of on-resistance, r dn is the pull-down driver resistance specified at 0.9 typical and r up is the pull-up driver resistance specified at 2 typical. v miller is the miller effective v gs voltage and is taken graphically from the power mosfet data sheet. the power mosfet input capacitance c miller is the most important selection criteria for determin - ing the transition loss term in the p-channel mosfet but is not directly specified on mosfet data sheets. c miller is a combination of several components, but it can be derived from the typical gate charge curve included on most data sheets (figure 4). the curve is the LTC3864 has internal filtering of the current sense voltage which should be adequate in most applications. however , adding a provision for an external filter offers added flexibility and noise immunity , should it be neces - sary. the filter can be created by placing a resistor from the r sense resistor to the sense pin and a capacitor across the v in and sense pins. power mosfet selection the LTC3864 drives a p-channel power mosfet that serves as the main switch for the asynchronous step- down converter. important p-channel power mosfet parameters include drain-to-source breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , gate-to-drain reverse transfer capacitance c rss , maximum figure 3. inductor current sensing figure 4. (a) typical p-mosfet gate charge characteristics and (b) test set-up to generate gate charge curve s d g v sd(test) r load i gate 3864 f04 miller effect q in a b c miller = (q b ? q a )/v sd(test) v sg ? + (a) (b) v in r sense LTC3864 v in sense r f mp optional filtering 3864 f03 c f LTC3864 3864fa
15 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion generated by forcing a constant current out of the gate of a common-source connected p-mosfet that is loaded with a resistor , and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-sour ce and gate-to-drain capacitances. the flat portion of the curve is the result of the miller multiplication effect of the drain- to-gate capacitance as the drain voltage rises across the resistor load. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v sd test voltage, but can be adjusted for different v sd voltages by multiplying by the ratio of the adjusted v sd to the curve specified v sd value. a way to estimate the c miller term is to take the change in gate charge from points a and b (or the parameter q gd on a manufacturers data sheet) and dividing it by the specified v sd test voltage, v sd(test) . c miller ? q gd v sd(test) the term with c miller accounts for transition loss, which is highest at high input voltages. for v in < 20v, the high- current efficiency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. schottky diode selection when the p-mosfet is turned off, a power schottky diode is required to function as a commutating diode to carry the inductor current. the average diode current is therefore dependent on the p-mosfets duty factor. the worst case condition for diode conduction is a short-circuit condition where the schottky must handle the maximum current as its duty factor approaches 100% (and the p-channel mosfets duty factor approaches 0%). the diode there - fore must be chosen carefully to meet worst case voltage and current requirements. the equation below describes the continuous or average forward diode current rating required, where d is the regulator duty factor. i f(avg) ? i out(max) ? 1?d ( ) once the average forward diode current is calculated, the power dissipation can be determined. refer to the schottky diode data sheet for the power dissipation p diode as a function of average forward current i f(avg) . p diode can also be iteratively determined by the two equations below, where v f(iout , tj) is a function of both i f(avg) and junction temperature t j . note that the thermal resistance ja(diode) given in the data sheet is typical and can be highly layout dependent. it is therefore important to make sure that the schottky diode has adequate heat sinking. t j ? p diode ? ja(diode) p diode ? i f(avg) ? v f(iout,tj) the schottky diode forward voltage is a function of both i f(avg) and t j , so several iterations may be required to satisfy both equations. the schottky forward voltage v f should be taken from the schottky diode data sheet curve showing instantaneous forward voltage. the forward voltage will increase as a function of both t j and i f(avg) . the nominal forward voltage will also tend to increase as the reverse breakdown voltage increases. it is therefore advantageous to select a schottky diode appropriate to the input voltage requirements. c in and c out selection the input capacitance c in is required to filter the square wave current through the p-channel mosfet. use a low esr capacitor sized to handle the maximum rms current. i cin(rms) ? i out(max) ? v out v in ? v in v out ? 1 the formula has a maximum at v in = 2v out , where i cin(rms) = i out(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple cur - rent ratings from capacitor manufacturers are often based on only 2000 hours of life, which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the ?v out is approximately bounded by: ? v out ? i l esr + 1 8 ? f ? c out ? ? ? ? LTC3864 3864fa
16 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion since ?i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, specialty polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. specialty polymer capacitors offer very low esr but have lower specific capacitance than other types. tantalum capacitors have the highest specific capacitance, but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long- term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvolt - age hazard to the power switch and controller. to dampen input voltage transients, add a small 5f to 40f aluminum electrolytic capacitor with an esr in the range of 0.5 to 2. high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of lead inductance. discontinuous and continuous operation the LTC3864 operates in discontinuous conduction (dcm) until the load current is high enough for the inductor current to be positive at the end of the switching cycle. the output load current at the continuous/discontinuous boundary i out(cdb) is given by the following equation: i out(cdb) ? (v in ? v out )( v out + v f ) 2 ? l ? f ? (v in + v f ) the continuous/discontinuous boundary is inversely proportional to the inductor value. therefore, if required, i out(cdb) can be reduced by increasing the inductor value. external soft-start and output tracking start-up characteristics are controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the internal 0.8v reference, the LTC3864 regulates the v fb pin voltage to the voltage on the ss pin. when the ss pin is greater than the internal 0.8v reference, the v fb pin voltage regulates to the 0.8v internal reference. the ss pin can be used to program an external soft-start function or to allow v out to track another supply during start-up. soft-start is enabled by connecting a capacitor from the ss pin to ground. an internal 10a current source charges the capacitor, providing a linear ramping voltage at the ss pin that causes v out to rise smoothly from 0v to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 0.8v 10a when the LTC3864 is configured to track another supply, a voltage divider can be used from the tracking supply to the ss pin to scale the ramp rate appropriately. two com - mon implementations of tracking as shown in figure 5a are coincident and ratiometric. for coincident tracking, make the divider ratio from the external supply the same as the divider ratio for the feedback voltage. ratiometric tracking could be achieved by using a different ratio than the feedback (figure 5b). note that the soft-start capacitor charging current is always flowing, producing a small offset error . to minimize this error, select the tracking resistive divider values to be small enough to make this offset error negligible. short-circuit faults: current limit and foldback the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the LTC3864, the maximum sense voltage is 95mv, measured across the inductor sense resistor r sense , placed across the v in and sense pins. the output current limit is approximately: i limit ? 95mv r sense ? ? i l 2 LTC3864 3864fa
17 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion the current limit must be chosen to ensure that i limit(min) > i out(max) under all operating conditions. the minimum current limit value should be greater than the inductor current required to produce maximum output power at worst case efficiency. worst-case efficiency typically oc- curs at the highest v in . short-circuit fault protection is assured by the combination of current limit and frequency foldback. when the output feedback voltage v fb drops below 0.4v, the operating frequency f will fold back to a minimum value of 0.18 ? f when v fb reaches 0v. both current limit and frequency foldback are active in all modes of operation. in a short- circuit fault condition, the output current is first limited by current limit and then further reduced by folding back the operating frequency as the short becomes more severe. short-circuit recovery and internal soft-start an internal soft-start feature guarantees a maximum posi - tive output voltage slew rate in all operational cases. in a short-cir cuit recover y condition for example, the output recovery rate is limited by the internal soft-start so that output voltage overshoot and excessive inductor current buildup is prevented. the internal soft-start voltage and the external ss pin operate independently. the output will track the lower of the two voltages. the slew rate of the internal soft-start voltage is roughly 1.2v/ms, which translates to a total soft-start time of 650s. if the slew rate of the ss pin is greater than 1.2v/ms the output will track the internal soft-start ramp. to assure robust fault recovery, the figure 5(a). two different modes of output tracking time coincident tracking external supply external supply v out voltage v out time 3864 f05a ratiometric tracking voltage figure 5(b): setup for ratiometric and coincident tracking r fb2 ext. v r fb1 coincident tracking setup to ss r fb2 v out to v fb r fb1 r1 ext. v r2 r1+ r2 r2 to ss r fb2 v out to v fb r fb1 3864 f05b ratiometric tracking setup 0.8v ext. v LTC3864 3864fa
18 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion internal soft-start feature is active in all operational cases. if a short-circuit condition occurs which causes the output to drop significantly, the internal soft-start will assure a soft recovery when the fault condition is removed. the internal soft-start assures a clean soft ramp-up from any fault condition that causes the output to droop, guar - anteeing a maximum ramp rate in soft-start, short-circuit fault release, or output recovery from drop out. figure 6 illustrates how internal soft-start controls the output ramp-up rate under var ying scenarios. guaranteed to operate down to a v in of 3.5v over the full temperature range. the implications of both the uvlo rising and uvlo falling specifications must be carefully considered for low v in operation. the uvlo threshold with v in rising is typi - cally 3.5v (with a maximum of 3.8v) and uvlo falling is typically 3.25v (with a maximum of 3.5v). the operating input voltage range of the l tc3864 is guaranteed to be 3.5v to 60v over temperature, but the initial v in ramp must exceed 3.8v to guarantee start-up. for example, figure 7 illustrates LTC3864 operation when an automotive battery droops during a cold crank condi - tion. the typical automotive battery is 12v to 14v, which is more than enough headroom above 3.8v for the l tc3864 to start up. onboard electronics which are powered by a dc/dc regulator require a minimum supply voltage for seamless operation during the cold crank condition, and the battery may droop close to these minimum supply requirements during a cold crank. the dc/dc regulator should not exacerbate the situation by having excessive dropout between the already suppressed battery voltage input and the output of the regulator which power these electronics. as seen in figure 7, the LTC3864s 100% duty cycle capability allows virtually no dropout (only the i out ? (r sense + r ds(on) ) drop across the sense resistor and p-mosfet if there is a significant i out ) from the battery to the output. the 3.5v guaranteed uvlo point assures sufficient margin for continuous, uninterrupted operation in extreme cold crank battery drooping conditions. however, additional input capacitance or slower soft start-up time may be required at low v in (e.g. 3.5v to 4.5v) in order to limit v in droop caused by inrush currents, especially if the battery or input source has a sufficiently large input impedance. figure 6. internal soft-start (a) allows soft start-up without an external soft-start capacitor and allows soft recovery from (b) a short-circuit or (c) a v in dropout figure 7. typical automotive cold crank v in undervoltage lockout (uvlo) the LTC3864 is designed to accommodate applications requiring widely varying power input voltages from 3.5v to 60v. to accommodate the cases where v in drops significantly once in regulation, the LTC3864 is 3864 f07 time v out v battery 12v LTC3864?s 100% duty cycle capability allows v out to ride v in without significant drop-out 5v voltage time ~ 650s (a) v out v in voltage 3864 f06 internal soft-start induced start-up (no external soft-start capacitor) time short-circuit (b) v out voltage internal soft-start induced recovery internal soft-start induced recovery time (c) v out v in v in dropout voltage LTC3864 3864fa
19 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion minimum on-time considerations the minimum on-time, t on(min) , is the smallest time duration that the LTC3864 is capable of turning on the power mosfet, and is typically 220ns. it is determined by internal timing delays and the gate charge required to turn on the mosfet. low-duty-cycle applications may approach this minimum on-time limit, so care should be taken to ensure that: t on(min) < v out v in(max) ? f if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will skip cycles. however, the output voltage will continue to regulate. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine the dominant contributors and therefore where efficiency improvements can be made. percent efficiency can be expressed as: % efficiency = 100% - (l1+l2+l3+) where l1, l2, l3, etc., are the individual losses as a per - centage of input power. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3864 application circuits. 1. i 2 r loss: i 2 r losses result from the p-channel mosfet resistance, inductor resistance, the current sense resis - tor, and input and output capacitor esr. in continuous mode operation the average output current flows through l but is chopped between the p-channel mosfet and the bottom side schottky diode. the following equation may be used to determine the total i 2 r loss: p i 2 r (i 2 out + ? i 2 l /12) ? [ r dcr + d ? (r ds(on) + r sense + r esr(cin) )] + ? i 2 l / 12 ? r esr(cout) 2. transition loss: transition loss of the p-channel mos - fet becomes significant only when operating at high input voltages (typically 20v or greater .) the p-channel transition losses (p pmostrl ) can be determined from the following equation: p pmostrl = v in 2 ? i out 2 ? ? ? ? ? ? ? (c miller ) ? r dn (v in ? v cap ) ? v miller + r up v miller ? ? ? ? ? ? ? f 3. gate charging loss: charging and discharging the gate of the mosfet will result in an effective gate charg - ing current. each time the p-channel mosfet gate is switched from low to high and low again, a packet of charge dq moves from the capacitor across v in C v cap and is then replenished from ground by the internal v cap regulator. the resulting dq/dt current is a current out of v in flowing to ground. the total power loss in the controller including gate charging loss is determined by the following equation: p cntrl = v in ? (i q + f ? q g(pmosfet) ) 4. schottky loss: the schottky diode loss is most signifi - cant at low duty factors (high step down ratios). the critical component is the schottky for ward voltage as a function of junction temperature and current. the schottky power loss is given by the equation below . p diode ? (1?d) ? i out ? v f(iout, t j) when making adjustments to improve efficiency, the in - put current is the best indicator of changes in efficiency. if changes cause the input current to decrease, then the efficiency has increased. if there is no change in input current, there is no change in efficiency . op ti-loop ? compensation opti-loop compensation, through the availability of the ith pin, allows the transient response to be optimized for a wide range of loads and output capacitors. the ith pin not only allows optimization of the control loop behavior LTC3864 3864fa
20 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion but also provides a test point for the step-down regulator s dc-coupled and ac-filtered closed-loop response. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at this pin. the ith series r ith -c ith1 filter sets the dominant pole-zero loop compensation. additionally, a small capacitor placed from the ith pin to signal ground, c ith2 , may be required to attenuate high frequency noise. the values can be modified to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the general goal of opti-loop compensation is to realize a fast but stable ith response with minimal output droop due to the load step. for a detailed explanation of opti-loop compensation, refer to application note 76. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im - mediately shifts by an amount equal to ? i load ? esr, where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. connecting a resistive load in series with a power mosfet, then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load-step condi - tion. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated feedback loop response. the gain of the loop increases with r ith and the bandwidth of the loop increases with decreasing c ith1 . if r ith is increased by the same factor that c ith1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor, c ff , can be added to improve the high frequency response, as shown in figure 1. capacitor c ff provides phase lead by creating a high frequency zero with r fb2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate overall performance of the step-down regulator. in some applications, a more severe transient can be caused by switching in loads with large (>10f) input capacitors. if the switch connecting the load has low resistance and is driven quickly, then the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifically for this purpose and usually incorporates cur - rent limiting, short-circuit protection and soft starting. design example consider a step-down converter with the following specifications: v in = 5v to 55v, v out = 5v, i out(max) = 2a, and f = 350khz (figure 8). the output voltage is programmed according to: v out = 0.8v ? 1 + r fb2 r fb1 ? ? ? ? ? ? if r fb1 is chosen to be 80.6k, then r fb2 would have to be 422k. LTC3864 3864fa
21 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion the freq pin is tied to signal ground in order to program the switching frequency to 350khz. the on-time required at 55v to generate a 5v output can be calculated as: t on = v out v in ? f = 5v 55v ? 350khz 260ns this on-time is larger than LTC3864s minimum on-time with sufficient margin to prevent cycle skipping. next, set the inductor value to give 60% worst-case ripple at maximum v in = 55v. l = 5v 350khz ? (0.6 ? 2a) ? ? ? ? 1? 5v 55v ? ? ? ? ? ? ? ? 10.8h select 10h, which is a standard value. the resulting maximum ripple current is: ? i l = 5v 350khz ? 10h ? ? ? ? 1? 5v 55v ? ? ?? ? ? ? ? 1.3a figure 8. design example (5v, 2a 350khz step-down converter) next, set the r sense resistor value to ensure that the converter can deliver a maximum output current of 2.0a with sufficient margin to account for component varia - tions and worst-case operating conditions. using a 30% margin factor: r sense ? 95mv 1.3 ? 2a + 1.3a 2 ? ? ? ? ? ? 27.5m ? use a more readily available 25m sense resistor. the current limit is: i limit ? 95mv 25m ? ? 1.3a 2 3.15a next choose a p-channel mosfet with the appropri - ate bv dss and i d rating. in this example, a good choice is the fairchild fdmc5614p (bv dss = 60v, i d = 5.7a, r ds(on) = 105m, 100c = 1.5, c miller = 100pf, ja = 60c/w). the expected power dissipation and the efficiency c ss 0.1f r run 100k r pgd 100k mp d1 sw l1 10h cap c cap 0.47f c in2 4.7f c in1 12f 63v pgnd LTC3864 3864 f08a ss ith freq sgnd run v in mode/plln sense gate pgood vfb r sense 25m r ith 9.53k r fb2 422k 47f 2 v out * 5v 2a r fb1 80.6k v in * 5.2v to 55v c vin 0.1f c ith1 3.3nf c ith2 100pf + c in1 : nichicon upj1j120mdd d1: diodes inc sbr3u100lp l1: toko 1217as-h-100m mp: fairchild fdmc5614p *v out follows v in when 3.5v v in 5.2v see dropout behavior in typical performance characteristics c ff 47pf load current (a) 0.01 50 efficiency (%) 80 70 60 90 100 0.1 1 3864 f08b pulse-skipping burst mode operation v in = 12v v out = 5v LTC3864 3864fa
22 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion resulting junction temperature for the mosfet can be calculated at t a = 70c, v in(max) = 55v and i out(max) = 2a: p pmos = 5v 55v (2a) 2 ? 1.5 ? 105m ? + (55v) 2 ? (2a / 2) ? 100pf ? 0.9 ? 8v ? 3v ? ? ? ? ? ? + 2 ? 3v ? 350khz 57mw + 90mw = 147mw t j = 70 c + 147mw ? 60 c/ w 80 c the calculations can be repeated for v in(min) = 5v: p pmos = 5v 5v (2a) 2 ? 1.5 ? 105m ? + (5.2v) 2 ? 100pf ? 0.9 ? 5.2v ? 3v + 2 ? 3v ? ? ? ? ? ? ? 350khz 630mw + 1mw 631mw t j = 70 c + 631mw ? 60 c / w 108 c next choose an appropriate schottky diode that will handle the power requirements. the diodes inc. sbr3u100lp schottky diode is selected (v f(2a,125c) = 0.5v, ja = 61c/w) for this application. the power dissipation and junction temperature at t a = 70c can be calculated as: p diode = 2a ? 1? 5v 55v ? ? ? ? ? 0.5v 909mw t j = 70 c + 909mw ? 61 c/ w = 125 c these power dissipation calculations show that careful attention to heat sinking will be necessary. for the input capacitance, a combination of ceramic and electrolytic capacitors are chosen to handle the maximum rms current of 1a. c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement. for this design, two 47f ceramic capacitors are chosen to offer low ripple in both normal operation and in burst mode operation. a soft-start time of 8ms can be programmed through a 0.1f capacitor on the ss pin: c ss = 8ms ? 10a 0.8v = 0.1f loop compensation components on the ith pin are chosen based on load step transient behavior (as described under opti-loop compensation) and is optimized for stability. a pull-up resistor is used on the run pin for fmea compli - ance (see failure modes and effects analysis). gate driver component placement, layout and routing it is important to follow recommended power supply pc board layout practices such as placing external power ele - ments to minimize loop area and inductance in switching paths. be careful to pay particular attention to gate driver component placement, layout and routing. th e effective c cap capacitance should be greater than 0.1f minimum in all operating conditions. operating voltage and temperature both decrease the rated capacitance to varying degrees depending on dielectric type. the LTC3864 is a pmos controller with an internal gate driver and boot- strapped ldo that regulates the differential cap voltage (v in C v cap ) to 8v nominal. the c cap capacitance needs to be large enough to assure stability and provide cycle- to-cycle current to the pmos switch with minimum series inductance. we recommend a ceramic 0.47f 16v capacitor with a high quality dielectric such as x5r or x7r. some high current applications with large qg pmos switches may benefit from an even larger c cap capacitance. figure 9 shows the LTC3864 generic application sche - matic which includes an optional current sense filter and s e ries gate resistor. figure 10 illustrates the recommended gate driver component placement, layout and routing of the gate, v in , sense and cap pins and key gate driver components. it is recommended that the gate driver layout follow the example shown in figure 10 to assure proper operation and long term reliability. LTC3864 3864fa
23 for more information www.linear.com/LTC3864 the LTC3864 gate driver should connect to the external power elements in the following manner. first route the v in pin using a single low impedance isolated trace to the positive r sense resistor pad without connection to the v in plane. the reason for this precaution is that the v in pin is internally kelvin connected to the current sense comparator, internal v in power and the pmos gate driver. connecting the v in pin to the v in power plane adds noise and can result in jitter or instability. figure 10 shows a single v in trace from the positive r sense pad connected to c sf , c cap , v in pad and c inb . the total trace length to r sense should be minimized and the capacitors c sf , c cap and c inb should be placed near the v in pin of the LTC3864. c cap should be placed near the v in and cap pins. figure 10 shows c cap placed adjacent to the v in and cap pins with sense routed between the pads. this is the recommended layout and results in the minimum parasitic inductance. the gate driver is capable of providing high peak current. parasitic inductance in the gate drive and the series in - ductance between v in to cap can cause a voltage spike between v in and cap on each switching cycle. the voltage spike can result in electrical over-stress to the gate driver and can result in gate driver failures in extreme cases. it is recommended to follow the example shown in figure 10 for the placement of c cap as close as is practical. r gate resistor pads can be added with a 0 resistor to allow the damping resistor to be added later. the total length of the gate drive trace to the pmos gate should be minimized and ideally be less than 1cm. in most cases with a good layout the r gate resistor is not needed. the r gate resistor should be located near the gate pin to re - duce peak current through gate and minimize reflected noise on the gate pin. the r sf and c sf pads can be added with a zero ohm resis - tor for r sf and c sf not populated. in most applications, external filtering is not needed. the current sense filter r sf and c sf can be added later if noise if demonstrated to be a problem. the bypass capacitor c inb is used to locally filter the v in supply. c inb should be tied to the v in pin trace and to the pgnd exposed pad. the c inb positive pad should connect to r sense positive though the v in pin trace. the c inb ground trace should connect to the pgnd exposed pad connection. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3864. 1. multilayer boards with dedicated ground layers are preferable for reduced noise and for heat sinking pur - a pplica t ions i n f or m a t ion c sf l1 q1 d1 cap c cap pgnd LTC3864 3864 f09 ss ith freq sgnd ground plane to pgnd run v in pllin/mode sense gate pgood v fb r ith r sf r sense r gate r freq r pgd r fb2 v out v in c in + ? c ith c pith c inb c ss c out r fb1 r gate to q1 gate to r sense + 3864 f10 c inb c cap gate sense cap v in c sf r sf to r sense ? figure 9. LTC3864 generic application schematic with optional current sense filter and series gate resistor figure 10. LTC3864 recommended gate driver pc board placement, layout and routing LTC3864 3864fa
24 for more information www.linear.com/LTC3864 poses. use wide rails and/or entire planes for v in , v out and gnd for good filtering and minimal copper loss. if a ground layer is used, then it should be immediately below (and/or above) the routing layer for the power train components which consist of c in , sense resistor, p-mosfet, schottky diode, inductor, and c out . flood unused areas of all layers with copper for better heat sinking. 2. keep signal and power grounds separate except at the point where they are shorted together. short signal and power ground together only at a single point with a narrow pcb trace (or single via in a multilayer board). all power train components should be referenced to power ground and all small signal components (e.g., c ith1 , r freq , c ss etc.) should be referenced to signal ground. 3. place c in , sense resistor, p-mosfet, inductor, and primary c out capacitors close together in one compact area. the junction connecting the drain of p-mosfet, cathode of schottky, and (+) terminal of inductor (this junction is commonly referred to as switch or phase node) should be compact but be large enough to handle the inductor currents without large copper losses. place the sense resistor and source of p-channel mosfet as close as possible to the (+) plate of c in capacitor(s) that provides the bulk of the ac current (these are normally the ceramic capacitors), and connect the anode of the schottky diode as close as possible to the (C) terminal of the same c in capacitor(s). the high di/dt loop formed by c in , the mosfet, and the schottky diode should have short leads and pcb trace lengths to minimize high frequency emi and voltage stress from inductive ringing. the (C) terminal of the primary c out capacitor(s) which filter the bulk of the inductor ripple current (these are normally the ceramic capacitors) should also be connected close to the (C) terminal of c in . 4. place pins 7 to 12 facing the power train components. keep high dv/dt signals on gate and switch away from sensitive small signal traces and components. 5. place the sense resistor close to the (+) terminal of c in and source of p-mosfet. use a kelvin (4-wire) con - nection across the sense resistor and route the traces together as a differential pair into the v in and sense pins. an optional rc filter could be placed near the v in and sense pins to filter the current sense signal. 6. place the resistive feedback divider r fb1/2 as close as possible to the v fb pin. the (+) terminal of the feedback divider should connect to the output regulation point and the (C) terminal of feedback divider should connect to signal ground. 7. place the ceramic c cap capacitor as close as possible to v in and cap pins. this capacitor provides the gate discharging current for the power p-mosfet. 8. place small signal components as close to their respec - tive pins as possible. this minimizes the possibility of pcb noise coupling into these pins. give priority to v fb , ith, and freq pins. use sufficient isolation when routing a clock signal into pllin /mode pin so that the clock does not couple into sensitive small signal pins. failure mode and effects analysis (fmea) a fmea study on the LTC3864 has been conducted through adjacent pin opens and shorts. the device was tested in a step-down application (figure 8) from v in = 12v to v out = 5v with a current load of 1a on the output. one group of tests involved the application being monitored while each pin was disconnected from the pc board and left open while all other pins remained intact. the other group of tests involved each pin being shorted to its adjacent pins while all other pins were connected as it would be normally in the application. the results are shown in table 2. for fmea compliance, the following design implementa - tions are recommended: ? if the run pin is being pull-up to a voltage greater than 6v, then it is done so through a pull-up resistor (100k to 1m) so that the pgood pin is not damaged in case of a run to pgood short. ? the gate of the external p-mosfet be pulled through a resistor (20k to 100k) to the input supply, v in so that the p-mosfet is guaranteed to turn off in case of a gate open. a pplica t ions i n f or m a t ion LTC3864 3864fa
25 for more information www.linear.com/LTC3864 a pplica t ions i n f or m a t ion table 2 failure mode v out i out i vin f recovery when fault is removed? behavior none 5v 1a 453ma 350khz n/a normal operation. pin open open pin 1 (pllin/mode) 5v 1a 453ma 350khz ok pin already left open in normal application, so no difference. open pin 2 (freq) 5v 1a 453ma 535khz ok frequency jumps to default open value. open pin 3 (gnd) 5v 1a 453ma 350khz ok exposed pad still provides gnd connection to device. open pin 4 (ss) 5v 1a 453ma 350khz ok external soft-start removed, but internal soft-start still available. open pin 5 (vfb) 0v 0a 0.7ma 0khz ok controller stops switching. v fb internally self biases hi to prevent switching. open pin 6 (ith) 5v 1a 507ma 40khz ok output still regulating, but the switching is erratic. loop not stable. open pin 7 (pgood) 5v 1a 453ma 350khz ok no pgood output, but controller regulates normally. open pin 8 (run) 5v 1a 453ma 350khz ok controller does not start-up. open pin 9 (cap) 5v 1a 453ma 350khz ok more jitter during switching, but regulates normally. open pin 10 (sense) 0v 0a 0.7ma 0khz ok sense internally prebiases to 0.6v below v in . this prevents controller from switching. open pin 11 (v in ) 5.4v 1a 597ma 20khz ok v in able to bias internally through sense. regulates with high v out ripple. open pin 12 (gate) 0v 0a 0.7ma 0khz ok gate does not drive external power fet, preventing output regulation. open pin 13 (pgnd) 5v 453ma 350khz ok pin 3 (gnd) still provides gnd connection to device. pins shorted short pins 1, 2 (pllin/mode and freq) 5v 1a 453ma 350khz ok burst mode operation disabled, but runs normally as in pulse-skipping mode. short pins 2, 3 (freq and gnd) 5v 1a 453ma 0khz ok freq already shorted to gnd, so regulates normally. short pins 3, 4 (gnd and ss) 0v 0a 0.7ma 0khz ok ss short to gnd prevents device from starting up. short pins 4, 5 (ss and vfb) 1v(dc) 3v p-p 50ma 9ma erratic ok v out oscillates from 0v to 3v. short pins 5, 6 (vfb and ith) 3.15v 625ma 181ma 350khz ok controller loop does not regulate to proper output voltage. short pins 7, 8 (pgood and run) 5v 1a 453ma 350khz ok controller does not start-up. short pins 8, 9 (run and cap) 5v 1a 453ma 350khz ok able to start-up and regulate normally . short pins 9, 10 (cap and sense) 0v 0a 181ma 0khz ok cap ~ v in , which prevents turning on external p-mosfet. short pins 10, 11 (sense and vin) 5v 1a 453ma 50khz ok regulates with high v out ripple. short pins 11, 12 (vin and gate) 0v 0a 29ma 0khz ok power mosfet is always kept off , preventing regulation. LTC3864 3864fa
26 for more information www.linear.com/LTC3864 typical a pplica t ions 24v to 60v input, 24v/1a output at 750khz efficiency 3.5v to 48v input, 1.8v/4a output at 100khz efficiency c ss 0.1f r pgd 100k mp d1 l1 10h cap c cap 0.47f c in2 10f 2 c in1 33f 63v pgnd LTC3864 3864 ta03a ss ith freq sgnd run v in mode/plln sense gate pgood v fb r sense 15m r ith 14k r freq 24.3k r fb2 102k 100f 2 v out 1.8v 4a 330f 6.3v r fb1 80.6k v in 3.5v to 48v c ith1 10nf + c in1 : sanyo 63me33ax d1: vishay v10p10 l1: wrth 7447709100 mp: vishay/siliconix si7461dp c vin 0.1f + c ith2 100pf r pgd2 768k mp d1 l1 47h cap c cap 0.47f c in2 2.2f c in1 33f 63v pgnd LTC3864 3864 ta02a ss ith c in1 : nichicon upj1j100mpd d1: diodes inc sbr3u100lp l1: toko 1217as-h-470m mp: vishay/siliconix si7113dn *v out follows v in when 3.5v v in 24v run v in mode/plln sense gate pgood v fb r sense 50m r ith 30.1k freq sgnd r freq 97.6k r fb2 887k 10f v out * 24v 1a r fb1 30.1k v in 24v to 60v c vin 0.1f c ith1 6.8nf c ith2 100pf r pgd1 200k + load current (a) 0.01 30 efficiency (%) 80 70 60 50 40 90 100 0.1 1 3864 ta02b pulse-skipping burst mode operation v in = 48v v out = 24v load current (a) 0.01 30 efficiency (%) 70 60 50 40 80 0.1 1 3864 ta03b pulse-skipping burst mode operation v in = 12v v out = 1.8v LTC3864 3864fa
27 for more information www.linear.com/LTC3864 r pgd2 549k mp d1 l1 22h cap c cap 0.47f c in2 4.7f c in1 33f 63v pgnd *v out follows v in when 3.5v v in 12v LTC3864 3864 ta04a ss ith freq sgnd run v in mode/plln sense gate pgood v fb r sense 30m r ith 11.3k r fb2 845k 10f 2 v out * 12v 2a r fb1 60.4k v in 12v to 58v c vin 0.1f c ith1 3300pf c ith2 100pf + c in1 : sanyo 63me33ax d1: diodes inc sbr3u100lp l1: toko 1217as-h-220m mp: vishay/siliconix si7465dp r pgd1 402k typical a pplica t ions 12v to 58v input, 12v/2a output at 535khz efficiency load current (a) 0.01 50 efficiency (%) 80 70 60 90 0.1 1 3864 ta04b pulse-skipping burst mode operation v in = 48v v out = 12v de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev d) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (ue12/de12) dfn 0806 rev d 3.30 0.10 0.25 0.05 0.50 bsc 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. LTC3864 3864fa
28 for more information www.linear.com/LTC3864 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (mse12) 0911 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev f) LTC3864 3864fa
29 for more information www.linear.com/LTC3864 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 6/14 modified v in to cap capacitance updated notes 2 and 3 1, 8, 10, 21, 25, 26, 28 2 LTC3864 3864fa
30 for more information www.linear.com/LTC3864 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2012 lt 0614 rev a ? printed in usa load current (a) 0.01 40 efficiency (%) 80 70 60 50 90 0.1 1 3864 ta05b pulse-skipping burst mode operation v in = 12v v out = 3.3v (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC3864 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3891 60v, low i q , synchronous step-down dc/dc controller phase-lockable fixed frequency 50khz to 900khz 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3890 60v, low i q , dual 2-phase synchronous step-down dc/dc controller phase-lockable fixed frequency 50khz to 900khz 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3824 60v, low i q , step-down dc/dc controller, 100% duty cycle selectable fixed frequency 200khz to 600khz 4v v in 60v, 0.8v v out v in , i q = 40a, msop-10e lt3845a 60v, low i q , single output synchronous step-down dc/dc controller synchronizable fixed frequency 100khz to 600khz 4v v in 60v, 1.23v v out 36v, i q = 120a, tssop-16 ltc3863 60v low iq inverting dc/dc controller pll fixed frequency 75khz to 750khz, 3.5v v in 60v C150v v out C0.4v, i q = 70a, 3mm 4mm dfn-12, msop-12 ltc3834/ltc3834-1 ltc3835/ltc3835-1 low i q , single output synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a/80a ltc3857/ltc3857-1 ltc3858/ltc3858-1 low i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle phase-lockable fixed frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a/170a ltc3859al low i q , triple output buck/buck/boost synchronous dc/dc controller all outputs remain in regulation through cold crank 2.5v v in 38v, v out(bucks) up to 24v, v out(boost) up to 60v, i q = 28a 3.5v to 38v input, 3.3v/3a output at 300khz efficiency r pgd 100k mp d1 l1 6.8h cap c cap 0.47f c vin 0.1f c in1 33f 63v pgnd LTC3864 3864 ta05a ss ith freq sgnd run v in mode/plln sense gate pgood v fb r sense 20m r ith 20k r freq 42.2k r fb2 634k 47f 2 v out 3.3v 3a r fb1 200k v in 3.5v to 60v c ith1 10nf c ith2 100pf c ss 0.1f + c in2 10f 2 c in1 : sanyo 63me33ax d1: vishay v15p45s l1: wrth 7447709100 mp: vishay/siliconix si7611dn LTC3864 3864fa

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